1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a synchronous semiconductor memory device capturing a command and inputting/outputting data synchronously with an externally input reference clock having a constant cycle.
2. Description of the Prior Art
FIG. 12 is a block diagram showing the structure of an operation control circuit of a conventional synchronous semiconductor memory device. Referring to FIG. 12, a reference clock circuit 1 receives an external reference clock signal extCLK and converts the same to an internal reference clock signal intCLK. A command decoder 2 decodes an external control signal and decides/designates operations of the synchronous semiconductor memory device. A control circuit part 3 receives decode signals from the command decoder 2 and controls internal operations of the synchronous semiconductor memory device.
The operations of the synchronous semiconductor memory device are generally classified into row system operations and column system operations. The row system operations mainly include a row system activating operation for selectively setting a word line high and amplifying the potential difference between a pair of bit lines with a sense amplifier, a refresh operation for rewriting data in a memory cell through a series of operations for activating a row system, setting the word line high and equalizing the pair of bit lines, a precharge operation for setting the word line low and equalizing the pair of bit lines, and the like.
The control circuit part 3 includes a row system activation trigger circuit 4 receiving a row system activation decode signal ACTF from the command decoder 2 and outputting a signal ACT triggering row system activation synchronous with the internal reference clock signal intCLK, a refresh trigger circuit 5 receiving a refresh decode signal REFF from the command decoder 2 and outputting a signal REF triggering a refresh operation synchronous with the internal reference clock signal intCLK, a precharge trigger circuit 6 receiving a precharge decode signal PREF from the command decoder 2 and outputting a signal PRE triggering a precharge operation synchronous with the internal reference clock signal intCLK, an internal RAS signal generation circuit 7 receiving the trigger signals ACT, REF and PRE and activating an internal row system basic signal RAS forming the basis of internal row system operations, and a row system.cndot.sense control circuit 8 receiving the internal row system basic signal RAS and controlling fine timings for individual row system operations such as a sense amplifier activation timing, an automatic precharge timing in the refresh operation and the like through an asynchronous delay circuit.
The internal row system basic signal RAS is activated in response to activation of the row system activation trigger signal ACT, and inactivated in response to activation of the precharge trigger signal PRE. In the refresh operation, the row system basic signal RAS is activated in response to activation of the refresh trigger signal REF, and automatically inactivated at a prescribed internal timing. This timing corresponds to an activation timing for a signal S0D output from the row system.cndot.sense control circuit 8 for instructing automatic precharge upon termination of a sense operation.
The automatic precharge signal S0D, which is activated in a precharge period, inhibits activation of the row system activation trigger signal ACT and the refresh trigger signal REF.
FIG. 13 is a timing chart showing the operations of the conventional synchronous semiconductor memory device shown in FIG. 12. Referring to FIG. 13, a signal COMMAND indicates a command decided by a combination of control signals externally input in the command decoder 2. With reference to FIG. 13, the synchronous semiconductor memory device executes the refresh operation in response to an external refresh command, and the internal row system basic signal RAS is incorrectly re-activated through a false external row system activation command IR.
Such a command not operation-assured in product specification is hereinafter referred to as an illegal command IR.
At a time T01, the refresh trigger circuit 5 captures data of the refresh decode signal REFF from the command decoder 2 in response to rise of the internal reference clock signal intCLK, and the refresh trigger signal REF goes high. In response to this change of the refresh trigger signal REF to a high level, the internal row system basic signal RAS output from the internal RAS signal generation circuit 7 goes high.
At a time T02, the refresh decoder signal REFF is already at a low level and hence the refresh trigger signal REF goes low in response to rise of the internal reference clock signal intCLK.
At a time T03, the signal S0D instructing starting of automatic precharge goes high. The period between the change of the internal row system basic signal RAS to a high level at the time T01 and termination of the sense operation at the time T03 is mainly designed by previously estimating the period between driving of a word line and termination of detection/amplification of the potential difference between a pair of bit lines by a sense amplifier and defined by the asynchronous delay circuit in the row system.cndot.sense control circuit 8. The row system basic signal RAS goes low in response to the instruction by the automatic precharge signal S0D for starting precharge.
At a time T04, a row system activation command (active command) is externally input as the illegal command IR. In response to the illegal command IR, the row system activation decode signal ACTF output from the command decoder 2 goes high. At the time T04, however, the automatic precharge signal S0D is high and hence the row system activation trigger signal ACT is not activated despite rise of the internal reference clock signal intCLK.
At a time T05, the automatic precharge signal S0D goes low to terminate the precharge period in the refresh operation.
The period between starting of the precharge operation at the time T03 and termination of the precharge operation at the time T04 is also designed on the basis of a period previously estimated as necessary for the precharge operation by simulation or the like, i.e., the period required for inactivating the word line and completing equalization of the pair of bit lines. In response to the change of the automatic precharge signal S0D to a low level, further, the row system activation trigger signal ACT is released from inhibition of activation, and activated to a high level. In response to this change of the row system activation trigger signal ACT, the internal row system basic signal RAS goes high again.
Thus, activation of the row system activation trigger signal ACT lags the rise of the internal reference clock signal intCLK. In the control circuit 3 operating synchronously with the clock signal having a high frequency, this delay thereafter causes various malfunctions such as displacement and mismatch of subsequent synchronous operations and the like.
In this case, further, not only the row system operations are reactivated immediately after termination of the precharge operation but also the internal row system basic signal RAS goes high with a noise-like shot depending on the high-level period of the row system activation trigger signal ACT responsive to the illegal command IR. Or, the internal row system basic signal RAS is continuously fixed high until an external precharge command is input.
In general, the word line is driven in response to rise of the internal row system basic signal RAS, and the driving of the word line is terminated in response to fall of the internal row system basic signal RAS.
The pair of bit lines are equalized to the same potential following fall of the word line potential, i.e., through control by previously setting the delay time. The word line and the pair of bit lines are connected with a plurality of memory cells as a matter of course, and have large load capacities inclusive of the capacities of the lines themselves. Therefore, a considerable time decided by the time constants (CR) of the word line and the pair of bit lines is required for charging/discharging the word line and the pair of bit lines having large load capacities. This time is by far longer than the rise and fall times of the internal reference clock signal intCLK. Further, the time required for charging/discharging the word line and the pair of bit lines having large load capacities remarkably varies with each device depending on the fabrication process, the operating temperature and the like.
If the row system operations are re-activated immediately after termination of the precharge operation as described above, it follows that the internal row system basic signal RAS goes high to re-drive the word line before the pair of bit lines equally reach a complete precharge potential together, due to dispersion of the device characteristics, the operating temperature and the like.
In this case, the word line is driven while the pair of bit lines are insufficiently precharged, to destroy data rewritten in the memory cells by the refresh operation. Further, the row system activation trigger signal ACT and the internal row system basic signal RAS activated with delays from rise of the internal reference clock signal intCLK also cause malfunctions or data destruction.
The illegal command IR is not assured in operation in the first place. If a malfunction occurs in the semiconductor memory device due to the illegal command IR, therefore, this malfunction is attributed to a false operation by the user. However, such a possibility may be unavoidable that the illegal command IR is input due to the structure of a system employing the semiconductor memory device or a program.
Providing for such a case, it is general for the provider of the semiconductor memory device to prevent malfunctions against the illegal command IR.
For example, Japanese Patent Laying-Open No. 9-153283 (1997) discloses a conventional synchronous semiconductor memory device having a structure inhibiting acceptance of command data in a refresh operation for coping with input of an illegal command. However, the synchronous semiconductor memory device described in Japanese Patent Laying-Open No. 9-153283 cannot prevent malfunctions against the illegal command IR input at the timing shown in FIG. 13.
When an illegal command instructing illegal row system activation or refresh is externally input immediately before termination of a precharge period or this time overlaps with the rise timing of the internal reference clock signal intCLK, therefore, the conventional synchronous semiconductor memory device having the aforementioned structure disadvantageously causes destruction of data stored in memory cells, a malfunction of the internal row system basic signal RAS, or various bad influences exerted by such malfunction.